1. Field of the Invention
This invention relates to double diffused MOS (DMOS) transistors. More particularly, the invention relates to a new DMOS device having a minimized on-voltage and processes for manufacture of such devices.
2. Description of the Prior Art
A typical, conventional DMOS device 1 is illustrated in FIG. 1. Device 1 is comprised of lightly N-doped epitaxial layer 2, heavily P-doped body regions 3 and 4, and heavily N-doped source regions 5 and 6. As is conventional with this type of device, the body and source regions are electrically connected with metallizations on the upper surface. In FIG. 1, such metallization section is indicated at 7 for body region 3 and source region 5. Metallization section 7 is electrically connected to a source terminal 9. Insulating layer 10, typically of silicon dioxide material, covers the central region of device 1. Gate electrode 11 is located on insulating layer 10, positioned above the central portion of device 1 and extends over channel regions 12 and 13. Electrical connection is made to gate 11 in the usual manner and brought out to gate terminal 14. Similarly, device 1 includes drain terminal 15 which is electrically connected to heavily N-doped region 16.
A typical DMOS transistor of the prior art, such as device 1, has a theoretical minimum voltage drop per unit area which is determined by the drain-to-source voltage (V.sub.DS) that it must sustain. This operating voltage sets both the minimum thickness and minimum resistivity of the epitaxial silicon region 2, between the bottom of the diffused body regions 3 and 4 and the heavily doped N+substrate 16 which is connected to drain terminal 15.
A variety of structures have been proposed to minimize the on-voltage of DMOS transistors and similar MOS-gated devices. The insulated gate bipolar transistor (IGBT) achieves a reduction in on-voltage by using a heavily doped substrate of conductivity type opposite to that of the epitaxial layer which injects carriers across the pn-junction into the lightly doped drain region, thus modulating the conductivity of this region. Although a reduction in on-voltage is obtained through this method, there is a diode offset in the current-voltage characteristics. Another problem with this attempted solution is that the presence of injected carriers increases the switching time of the IGBT. Additionally, care must be taken not to inadvertently activate the parasitic NPN-PNP structure, or latch-up will occur.
Another approach for reducing the on-voltage of DMOS transistors is to include a separate region that may be biased to inject carriers into the lightly doped drain region. Such a device is illustrated in FIG. 2 and is indicated by reference character 1a . Device 1a differs from device 1 of FIG. 1 by the addition of highly P-doped region 17, which is positioned remote from the channel regions 12a and 13a, and which is separately biased. There are several disadvantages to device 1a, the first of which is that injection of minority carriers into the drain region reduces switching speed since these carriers must either be removed by fields at the terminals or must recombine before the device may be switched off. A further disadvantage is the presence of the P-type region that injects holes into the N-type drain region, since this arrangement can lead to inadvertent latch-up because of the lateral PNPN structure.
Another attempt to reduce the on-voltage of a DMOS device is illustrated in U.S. Pat. No. 4,630,084 to Tihanyi, issued Dec. 16, 1986. In the Tihanyi device a P-type injecting region is equally spaced between adjacent channel regions and this injecting region is electrically connected to the gate. There are several disadvantages to this attempted solution in the reduction of on-voltage. With the gate tied to the P-injecting region, the gate no longer has a high impedance characteristic of a normal DMOS transistor and both the input impedance and the amount of current injected are determined by the resistance connected between the gate terminal and the P-injector region. With the gate biased positive with respect to the drain, injected carriers modulate the conductivity of the lightly doped drain region. The injection of minority carriers in a drain region reduces the switching speed of this device because these carriers must either recombine or be removed by fields at the terminals before the device can be fully turned off. Yet another disadvantage of the Tihanyi type device is that the presence of the P-type region that injects holes into the N-type drain region may lead to an inadvertent latch-up condition because of the presence of the lateral PNPN structure. Looking at the device in Tihanyi, the PNPN structure is found by observing that the injector is P-type, the drain zone N-type, the channel is of P-type material and finally the source consists of N-type material. With this configuration, if the product of the current gains of the PNP and the NPN transistor exceeds one, the potential exists for latch-up to occur.